Formally Verifying Analog Neural Networks Under Process Variations Using Polynomial Zonotopes

arXiv:2605.10474v2 Announce Type: replace-cross Abstract: Analog neural networks are gaining attention due to their efficiency in terms of power consumption and processing speed. However, since analog neural networks are implemented as physical circuits, they are highly sensitive to manufacturing process variations, which can cause large deviations from the nominal model. We present a polynomial-based model that resembles the performance of the neuron circuit under process variations. This model is formally verified via reachability analysis using polynomial zonotopes, thus avoiding conventional, time-consuming Monte Carlo simulations. We evaluate our proposed verification approach on three different datasets and on fully-connected and convolutional analog neural networks. Our experimental results confirm the effectiveness of our verification approach by reducing the verification time from up to a day to seconds while enclosing up to 99% of the variation samples.